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上海腾希电气技术有限公司
主营：西门子PLC,V90伺服,V20变频器
上海腾希电气技术有限公司
主营：西门子PLC,V90伺服,V20变频器
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The Oversampling DQ function outputs 32 ** states at equal intervals per application cycle (for example OB 91, OB 6x). Up to 32 edges are therefore possible per application cycle at a given digital output. The 32 states are set over the control interface. The output occurs synchronously with time TO (setpoint transfer).
提示 Isochronous modeOversampling requires isochronous mode. |
The image below is an example of oversampling of DQ5:
TAPP | Application cycle |
MSB | Most significant bit |
LSB | Least significant bit |
提示 Output frequency with the Oversampling functionThe combination of application cycle and the 32-bit string output must not result in an output frequency that exceeds the maximum switching frequency for the digital outputs. |
Select the operating mode Oversampling DQ for the required channel.
图片: Oversampling DQ
提示 Extending the configuration limitsA maximum of eight oversampling DQ can be configured at the inputs/outputs of the X142 interface. If the oversampling DQ at X142 are not sufficient for your needs, you can increase the configuration limits with time-based IO modules, for example: ET 200SP distributed I/O system: TM Timer DIDQ 10x24V ET 200MP distributed I/O system: TM Timer DIDQ 16x24V You can find more information on these systems in . |
You can invert the 24 V ** to adjust it to the process. By default, the ** is not inverted.
If you select the high-speed output option, the digital output is switched alternately to 24 V DC and ground. Allows for extremely steep edges (output delay in the 1 μs range).
To allow **s pending very briefly to be output by oversampling DQ (for example level of 0.1 ms), you must operate the output as a high-speed output.